The present application relates to semiconductor device manufacturing, and more particularly to methods of forming patterns within an interconnect structure that have a reduced critical dimension.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene interconnect structures. The interconnect structure typically includes copper, Cu, or a Cu alloy since Cu-based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al-based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) is achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0.
During the formation of interconnect structures, the interconnect conductive metal, e.g., copper, is typically formed within an opening, e.g., line and/or via, which is present in an interconnect dielectric material. The opening that is provided within the interconnect dielectric material is typically formed utilizing lithography and etching. The resolution of the pattern that is provided by current lithography techniques is limited to 30 nm; below 30 nm the resolution of current lithography is poor.
As such, there is a need to provide a method that is able of forming interconnect structures in which the pattern that is formed within the interconnect dielectric material is reduced below the resolution limit of current lithography techniques.